1. Field of the Invention
The present invention relates to a phase locked loop circuit and more particularly relates to a phase locked loop circuit with a damping factor control circuit.
2. Description of the Prior Art
In the past few years, PLL (phase locked loop) frequency synthesizer tuners, which use PLL circuits as local oscillation circuits, have been generally employed. Such tuners have enjoyed considerable use in portable FM radio receivers. In such tuner, when it is desired to receive a particular broadcast station at a given frequency, the frequency dividing ratio N of a programmable divider in the PLL circuit is selected to correspond to the frequency of the desired broadcast station. In this case, the frequency is selected from a broadcast band of, for example, 76.1 MHz to 89.9 MHz in Japan, 87.9 MHz to 107.9 MHz in the United States, and 87.5 MHz to 108 MHz in Europe. Therefore, if a "world traveller" type FM receiver is constructed so that both the frequency band of Japan and that of the United States are to be spanned, the range of possible dividing ratios becomes rather large. However, the damping factor of the PLL circuit is lowered by any significant increase of the dividing ratio N and, as a result, the frequency synthesizer tuner in such an FM receiver might be unable to stably lock onto the frequency of the desired FM station.
Heretofore, there has not been proposed a PLL circuit including a damping factor control circuit to avoid the above defect, and which would be sufficiently simple in construction to justify its use in a portable FM receiver.